1. Field of the Invention
The present invention relates to a liquid crystal display apparatus, in particular to an active matrix type liquid crystal display apparatus in which switching elements are arranged in a matrix form on a substrate.
2. Description of the Related Art
Conventionally, a liquid crystal display apparatus using a nematic liquid crystal is widely used for segment type liquid PC; crystal display apparatuses such as watches or calculators. Recently, taking advantages of its reduced size in thickness, light weight and low power consumption, the liquid crystal display apparatus is widely used for any kind of display device of word processors, computers, navigation systems or the like. In particular an active matrix type liquid crystal display apparatus has been widely used, in which an active element such as a thin film transistor (hereinafter referred to as TFT) is used as a switching element and pixels are arranged in a matrix form.
A liquid crystal display apparatus, in comparison with CRT (cathode ray tube) conventionally used as a display, has advantages of remarkably reduced thickness (depth), low power consumption and ease of full color display, and is in increasing demand in a variety of fields including personal computers, monitors, mobile televisions and camera display devices.
FIG. 16 is a view showing a schematic structure of a conventional active matrix type liquid crystal display apparatus. The liquid crystal display apparatus is transparent type and has a light-transmitting active matrix substrate on which a plurality of pixel electrodes 101 for applying a voltage to a liquid crystal layer are formed in a matrix form. As a switching element for selectively driving pixel electrodes 101, a TFT 102 is formed on the active matrix substrate, whose drain terminal is connected to a pixel electrode 101. Furthermore, in order to display in color, on the active matrix substrate or on a counter substrate are provided color filter layers such as red, green and blue.
To a gate terminals of the TFT 102 is connected a scanning line 103. In addition, a gradation signal line 104 is connected to a source terminal. The scanning line 103 and the gradation signal line 104 are arranged so as to pass the periphery of the pixel electrode 101 and intersect at right angles each other. When a signal is inputted via the scanning line 103,to the gate terminal, the TFT 102 is driven and controlled. When an input signal is inputted to obtain continuity between the source terminal and the drain terminal, a data signal supplied via a gradation signal line 104 is inputted as a display signal to the pixel electrode 101.
To the drain terminal of the TFT 102 is connected one terminal of an additive capacitance 105 in conjunction with pixel electrodes 101. The other terminal of the additive capacitance 105 is connected to a common signal line 106 and the additive capacitance 105 plays a role for keeping a voltage applied to a liquid crystal layer. Since the capacitance of the additive capacitance 105 Cs causes a signal delay, in order to reduce the signal delay a connecting line 107 for connecting common signal lines 106 can be provided. The inventors of the invention disclose the connecting line 107 which connects the common signal lines 106 in Japanese Unexamined Patent Publication JP-A 3-72321 (1991).
In Japanese Unexamined Patent Publication JP-A 3-72321 (1991), common main wirings for electrically connecting between storage capacitance (Cs) bus lines are provided at both ends of the Cs bus lines, whereby the signal delay is reduced and high image quality can be obtained.
In the active matrix type liquid crystal display apparatus, a liquid crystal layer having a thickness of 4.3 to 4.5 xcexcm in general is sandwiched between an active matrix substrate and an opposite counter substrate to form a liquid crystal capacitance 108. The additive capacitance 105 is connected to the liquid crystal capacitance 108 in parallel. However, the conventional structure as shown in FIG. 16 has problems such as increasing possibility of occurrence of failure, decreasing yield and increasing manufacturing costs because there is a intersection part between the scanning line 103 and the gradation signal line 104. Furthermore, with the conventional structure a capacitance is formed in the intersection part of signal lines via an insulating film, and a signal delay such as a common signal delay occurs, which may reduce display quality of a liquid crystal display apparatus.
FIG. 17 is a view showing a schematic configuration of a liquid crystal display apparatus having a counter source structure which is proposed in U.S. Pat. No. 4,694,287. Since in this structure on the TFT substrate side there is no intersection part of signal lines, a leak between signal lines hardly occurs and since intersection parts are -not on the same substrate, a capacitance added to signal lines can be reduced. In the case of the counter source structure, on the pixel substrate on which pixel electrodes are formed, scanning lines and gradation signal lines, which are formed on the different substrate, do not intersect, whereby reduction of the probability of occurrence of line failure, enhancement of yield and reduction of manufacturing costs can be realized. In addition, in the case of the counter source structure, there is no intersection of signal lines on the same substrate, therefore no capacitance is formed in the intersection part. Accordingly, in comparison with the conventional structure as shown in FIG. 16, the capacitance added to signal lines and the signal delay can be reduced.
In the counter source structure as shown in FIG. 17, on the pixel substrate 110 are arranged switching elements 111 with three terminals such as amorphous silicon semiconductors are arranged in a matrix form to form an active matrix. The switching element 111 is, for example, a TFT, to a gate terminal of which is connected a scanning line 112 for each of columns of switching element, and to a source terminal of which is connected a reference signal line 113 for each of the columns of switching elements, and to a drain terminals of which is connected a pixel electrode 114. On a counter substrate 115 opposite to a pixel substrate are arranged a plurality of gradation signal lines 116 in a direction orthogonal to the scanning line 112. The gradation signal line 116 also serves as a counter electrode in an opposite part to the pixel electrodes 114.
The liquid crystal display apparatus, taking advantages of reduced thickness, light weight and low power consumption, is widely used for any kind of display devices such as televisions, computers and navigation systems. Demand for upsizing of display and high resolution of panels is increasing through the years. In order to achieve an upsized high resolution panel, it is necessary to solve a problem of signal delay, which is one of the biggest problems to be solved. With the upsizing of the panel, the signal line will be longer and the resistance value of the signal line and the capacitance value added to the signal line will increase. Since the extent of signal delay is proportional to the product of resistance value and capacitance value, upsizing of panels involving increases of both the resistance value and the capacitance value, causes a greater signal delay. As a result, within writing time a desired voltage can not be applied to a part of liquid crystal, which causes degradation in display quality, so-called shadowing.
Similarly, in enhancing the resolution, the signal writing time is also reduced and an effect of signal delay will appear strongly. Consequently, the same as in the case of upsizing the panel, degradation in display quality will occur.
Moreover, in the case of upsizing the display panel and enhancing the resolution, the following is unavoidable:
1) the resistance value of the signal line is increased;
2) the capacitance added to the signal line is increased; and
3) the writing time is reduced.
Therefore it is difficult to solve the problem of signal delay under such conditions.
In order to decrease the signal delay, the following solutions are considered:
1) to increase the thickness of a laminated metal film which forms the signal line in order to reduce the signal line resistance;
2) to increase the width of the signal line in order to reduce the resistance of the signal line; and
3) to increase the distance between the signal lines to reduce the capacitance added to the signal lines in the case of a counter source structure.
The solution 1), however, causes longer film producing time, namely reduction in manufacturing capacity, because the laminated metal film is thicker than the conventional film. Additionally, control of patterning process by etching will be more difficult, and as well degradation in quality of the liquid crystal display apparatus and increase in manufacturing costs are caused. With regard to the solutions 2) and 3), by increasing the width of the signal line or the distance between the signal lines, the area of pixel electrode will be decreased and accordingly the opening rate of a liquid crystal panel is reduced. With the reduction of the opening rate, the brightness of the liquid crystal panel as a display panel will be reduced and display quality is degraded. Therefore, these solutions cause adverse effects such as yield reduction, degradation in display quality due to the opening rate reduction and increase of manufacturing costs.
In particular, with the conventional structure as shown in FIG. 16, in the intersection part of signal lines via an insulating film, a capacitance is formed and accordingly a capacitance added to the signal line will be increased. As a result, the signal delay will be longer, and accordingly the signal delay which is caused in upsizing of liquid crystal display panel and increasing of resolution, will become a very serious problem. In a liquid crystal display apparatus of a counter source structure as shown in FIG. 17, there is no intersection part of signal lines on the same substrate whereby the capacitance added to signal lines can be reduced in comparison with the case of a conventional structure, and the signal delay can be suppressed. However, with upsizing of liquid crystal panel and increasing of resolution, it will become very difficult to manufacture without degradation in display quality and increase of manufacturing costs.
In an upsized liquid crystal display panel of high resolution, it is difficult to suppress the signal delay only by electrical connection at both ends of the Cs bus line, as disclosed in Japanese Unexamined Patent Publication JP-A 3-72321 (1991). As prior art in, even if a counter source structure is employed to avoid an occurrence of leakage between signal lines or reduce the additive capacitance, as shown in U.S. Pat. No. 4,694,287, the degradation of display quality can not be suppressed, which is caused by a signal delay with upsizing the liquid crystal display panel and enhancing the resolution.
The applicant proposes a liquid crystal display apparatus in Japanese Unexamined Patent Publication JP-A 11-311807 (1999), comprising a counter source structure without horizontal shadowing and with high display quality. In the liquid crystal display apparatus proposed in Japanese Unexamined Patent Publication JP-A 11-311807 (1999), a plurality of reference signal lines are interconnected via the first connecting line. And a plurality of reference signal lines are also connected to input terminals of reference signals via two drawing lines connected to the first connecting lines. The first connecting line and both drawing lines are arranged on the substrate outside from an image display region in which pixel electrodes are formed. In the liquid crystal display apparatus, reference signals can be inputted only from input terminals on the substrate on which pixel electrodes are formed.
An object of the present invention is to provide a liquid crystal display apparatus, which realizes enhancement of display quality at low cost regardless of an upsizing and high resolution realization.
The invention provides a liquid crystal display apparatus comprising:
a pixel substrate;
a counter substrate disposed opposite to the pixel substrate; and
a liquid crystal layer sandwiched therebetween, the pixel substrate comprising thereon:
a plurality of switching elements provided with a control terminal and first and second controlled terminals, a conductive state between the first and second controlled terminals, being controlled according to a signal inputted to the control terminal, the plurality of switching elements being arranged in a matrix form;
a plurality of scanning lines for connecting the control terminals of the respective switching elements for each row thereof;
a plurality of reference signal lines for connect the first controlled terminals of the switching elements for each row thereof; and
a plurality of pixel electrodes which are connected to the second controlled terminals of the switching elements, the counter substrate comprising thereon:
a plurality of counter electrodes, which are disposed opposite to respective pixel electrodes; and
a plurality of signal lines for connecting the counter electrodes for each column thereof,
the liquid crystal display apparatus further comprising:
a pixel side connecting region which is formed on the pixel substrate and is connected to the plurality of reference signal lines;
a counter side connecting region which is formed on the counter substrate so as to oppose to the pixel side connecting region; and
conductive material for electrically connecting between the pixel side connecting region and the counter side connecting region.
According to the invention, the liquid crystal display apparatus is formed in which the liquid crystal layer is sandwiched between the pixel substrate and the counter substrate. On the pixel substrate, the plurality of switching elements, the plurality of scanning lines, the plurality of reference signal lines, and the plurality of pixel electrodes are provided. On the counter substrate, the plurality of counter electrodes and the plurality of signal lines are provided. On the pixel substrate, the pixel side connecting region is formed which is connected to the plurality of reference signal lines. On the counter substrate, the counter side connecting region is formed so as to oppose to the pixel side connecting region. Since between the pixel side connecting region and the counter side connecting region are electrically connected by conductive material, the signal delay can be reduced. In addition, since on the pixel substrate, the scanning lines and reference signal lines are respectively formed in a row direction, there is no intersection part on the pixel substrate, and the gradation signal lines which intersect scanning lines at right angles in a column direction, can be formed on the counter substrate, whereby reduction of the probability of line failure occurrence and enhancement of yield can be achieved, with the result that manufacturing costs can be reduced.
As mentioned above, according to the invention, the scanning lines and the gradation signal lines do not intersect each other on the pixel substrate because the scanning lines and the gradation signal lines are respectively formed on different substrates, namely, on the pixel substrate and the counter substrate. Accordingly reduction of the probability of line failure occurrence and enhancement of yield can be achieved, with the result that manufacturing costs can be reduced. Furthermore, since a reference signal can be inputted from the counter substrate side via conductive material to the reference signal lines on the pixel substrate, it is possible to reduce the reference signal delay, prevent shadowing due to a signal delay and enhance display quality. With this structure, without changing wiring material for forming signal lines in the display region, and the thickness and width of the signal lines, the signal delay can be reduced, and therefore without reducing the opening rate and reference signal delay, enhancement of display quality can be realized. In addition, since the reference signal delay can be reduced, it is possible to reduce the width of the reference signal line and increase the opening rate to further enhance the display quality. It is also possible to reduce the film thickness and manufacturing costs of the liquid crystal display apparatus to increase productivity.
In the invention it is preferable that the pixel substrate comprises a main reference signal line for connecting the plurality of reference signal lines, disposed outside a region where the plurality of pixel electrodes are arranged, and the pixel side connecting region is formed on the main reference signal line.
According to the invention, since the main reference signal line for connecting between the plurality of reference signal lines are disposed outside the region of the pixel substrate where the pixel electrodes are arranged, and the pixel side connecting region is formed on the main reference signal line, it is possible to increase the area of the pixel side connecting region, and reduce the resistance value and signal delay. Further, in the case where the signal delay in the pixel side connecting region is reduced, it is also possible to reduce the width of the reference signal line and increase the opening rate in the region where the pixel electrodes are arranged, to enhance display quality. Additionally, it is also possible to decrease the film thickness of the reference signal line to increase productivity, with the result that the price of the liquid crystal display panel is reduced.
As mentioned above, according to the invention, since the pixel side connecting region is provided on the main reference signal line disposed in the region of the pixel substrate where the pixel electrodes are formed, by increasing the width of the main reference signal line or the film thickness, an electrical resistance and signal delay can be reduced.
In the invention it is preferable that the combination of the pixel side connecting region, the counter side connecting region and the conductive material is formed at a plurality of points.
According to the invention, since the electrical connection to the reference signal lines are made at a plurality of points, the signal delay can be reduced. As mentioned above, according to the invention, the electrical connection from the counter substrate to the reference signal lines is made at a plurality of points, the signal delay of the reference signal which is inputted to the reference signal line can be further reduced, shadowing due to the signal delay can be prevented, with the result that display quality can be enhanced.
In the invention it is preferable that a plurality of pieces of the conductive material are arranged for a single combination of the pixel side connecting region and the counter side connecting region.
According to the invention, since the plurality of pieces of the conductive material are used for connection between the pixel side connecting region and the counter side connecting region, even if a poor electrical connection occurs in any one of the pieces of the conductive material, the other pieced can ensure the electrical connection, and reliability thereof can be improved. As mentioned above, according to the invention, since the plurality of pieces of the conductive material are used for connection between the pixel side connecting region and the counter side connecting region, the reliability of the electrical connection can be improved and the electrical resistance and signal delay can be reduced.
In the invention it is preferable that the liquid crystal display apparatus further comprises a control substrate, which is connected to the counter side connecting region, for inputting the reference signal to the reference signal lines via the conductive material and the pixel side connecting region.
According to the invention, the reference signal can be inputted with a reduced delay time from the control substrate via the counter side connecting region to the reference signal lines on the pixel substrate, and therefore the signal delay can be suppressed with the result that display quality can be improved. As mentioned above, according to the invention, the reference signal can be inputted with a reduced delay time from the control substrate to the reference signal lines, with the result that display quality can be improved.